There is a growing demand for integrated circuits to be provided with different voltages for internal distribution according to which of their operative phases are to be activated. For example, semiconductor non-volatile storage devices (such as Flash, EPROM, E.sup.2 PROM memories), require different internal voltages for wordline biasing at different phases of the device operation. For a NORed memory, for instance, a reading operation involves biasing the wordline of the addressed cell to a voltage equal to the supply voltage (V.sub.dd =3V or 5V), whereas that same wordline is to be applied suitably higher voltages (e.g., V.sub.pp =12V) during the programming phase; V.sub.dd being a voltage supplied from outside the device, and V.sub.pp either a voltage supplied from outside or produced inside from V.sub.dd. Furthermore, for multilevel EPROM storage devices, the wordline bias voltage during the read phase is a higher value than the supply voltage V.sub.dd (being usually of 3V or 5V). In fact, for a larger number of levels than two to be reliably allocated, the range of possible cell currents must be stretched to values of 100 to 120 .mu.A. Such current values can only be obtained, however, by using gate voltages in the 5V to 6V range. In addition, during specific operative phases (such as those activated for testing), the wordline of the selected cell is to be brought to an analog voltage ranging from 0 to V.sub.pp for DMA (Direct Memory Access) reading, as those skilled in the art will recognize.
Accordingly, integrated circuits that are to operate in this way must be provided internally with a selector switch, to each time pick up and distribute an appropriate voltage to the working blocks, under control by suitable control signals.
A prior art electrically programmable non-volatile memory cell device 2 is shown in FIG. 1. The memory cell device 2 includes a selector switch 4, a row decoder 6, and a set of final decoding stages 8 for biasing respective word lines of a memory cell matrix (not shown) as needed for the differential operational phases of the memory cell device, such as reading, programming, and DMA reading.
Specifically with a non-volatile memory, there are essentially two voltages (referenced LV and HV hereinafter) involved, and the selector switch 4 is mainly concerned with biasing the wordlines. In this case, the selector switch will switch the power supply to the final decoding stages 8, as shown in FIG. 1, between the low voltage LV and the high voltage HV, according to whether the addressed cell is to be read or programmed, respectively.
It can be appreciated that, if positive voltages are to be output to the selector switch with no voltage drops, the use of p-channel pass transistors becomes mandatory. In the instance of n-well CMOS technology, the use of p-channel transistors within the selector switch creates quite a few problems because the source and drain regions of the transistors must be reverse biased, relative to the wells wherein the p-channel transistors are formed, all the time. Thus, the well regions would have to be connected to that terminal of their associated transistor which is at the highest voltage value.
However, as described in further detail hereinafter, it often is impossible to identify the highest voltage terminal of the p-channel transistors which make up the selector switch, because of its dependence on the specific operative phase being activated. A first simple circuit diagram of the selector switch is shown in FIG. 2 and includes just two p-channel transistors (P1 and P2) which are driven by a control signal PH for turning on either transistor to the exclusion of the other.
It is readily seen, however, that this simple approach rules out the possibility of using HV&lt;LV, since there would occur forward biasing between the well region of P1 and the drain region of this transistor.
This is an important limitation placed on non-volatile storage devices, because proper operation of the selector switch cannot be assured in such modes as DMA testing and reading. In fact, the operation specifications usually provide for the user's ability to set up at will the value of HV during the read phases, with the single stipulation that it should not exceed the value of the supply voltage V.sub.dd. In addition, considerations of constructional simplicity point to the advisability of having the DMA mode implemented through the HV terminal for accessing the node OUT of the selector switch directly. During such operations, the applied voltages may take values in the range of 0V to 12V.
Thus, the value of HV can drop below that of LV in both the DMA testing and the reading modes, and this prior approach tends to be used in a less degree.
On the other hand, the problem can be solved by using more complicated schemes, with 3 or 4 transistors and a peculiar interconnection of the wells, like that shown schematically in FIG. 3 for a three-transistor construction.
But these prior approaches, when applied to commercial devices of the EPROM type, are ill-suited for use in applications where the switching rate of the selector switch (and hence of the voltage at the node OUT) is a parameter of major consideration. In fact, the use of such circuit constructions brings about a problem of transient control of the common node N of the transistors P1 and P3. This node evolves, because of the great difference in capacitive load between it and the output terminal OUT (up to approximately 800 pF in a 4096-row memory), toward the voltage HV, upon switching the output node OUT from LV to HV (P1 and P3 being both turned on), at a definitely higher rate than the output node, so that the n-p junction formed of the N region and the well of P3 becomes forward biased.
Unfortunately, the circuit setups currently investigated to limit this bias effect invariably result in the LV/HV switching time at the output node being increased. The significance of this problem can be appreciated by considering that the program algorithm for a non-volatile memory cell (also referred to as the program-and-verify algorithm) involves the application, to the selected wordline, of a large number of high-voltage pulses, regularly interspersed with an equal number of low-voltage pulses, during which the programmed state of the cell is verified.
On the other hand, during each HV-to-LV switch of the node OUT (P1 and P3 being turned off, P2 being turned on), the problem arises that the two transistors P1, P3 cannot be turned off simultaneously. In fact, the value of HV would then remain "stored" dynamically in the intermediate node N, while the output node goes quickly to LV; here again, the n-p junction between the N region and the well of P3 becomes forward biased.
Therefore, during the HV-to-LV switching transient of the node OUT, P1 should be turned off first (in order to isolate the node N from HV), and P3 only turned off after a while (i.e., once the voltage at OUT has attained the value of LV). In this way, N and OUT are "equalized" during the transient through the transistor P3, still on.
Accordingly, the phase edges of the control signals PH and PH' must have an interval (on the order of a few .mu.s) of non-overlap, thereby introducing unavoidable delay in the overall switching time.
Thus, the prior solutions do not suit applications which require very fast (e.g., on the order of 100-200 ns) switching of the node OUT between the voltages HV and LV.